Ingo Molnar wrote:
> > > How about this patch? Instead of making a per-cpu trampoline, write to
> > > the msr during each context switch.
> >
> > I wanted to avoid slowing down the context switch, but I didn't actually
> > time how much the MSR write hurts you (it needs to be conditional,
> > though, I think).
>
> this is the solution i took in the original vsyscall patches. The syscall
> entry cost is at least one factor more important than the context-switch
> cost. The MSR write was not all that slow when i measured it (it was on
> the range of 20 cycles), and it's definitely something the chip makers
> should keep fast.
I think it would be better to make NMI and Debug trap use task gates,
if that does actually work, and let the NMI and debug handlers fix the
stack if they trap in the entry paths. They are much rarer after all.
My unreliable memory recalls about 40 cycles for an MSR write on my Celeron.
However, I think you still need MSR writes _sometimes_ in the context
switch to disable sysenter for vm86-mode tasks.
Could the context switch be written like this?:
if (unlikely((prev_task->flags | next_task->flags) & PF_SLOW_SWITCH)) {
// Do rare stuff including debug registers
// and sysenter/syscall MSR change for vm86.
}
// Other stuff.
-- Jamie
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This archive was generated by hypermail 2b29 : Mon Dec 23 2002 - 22:00:29 EST