I was looking at some new hardware and noticed that it's
got explicit support for the PCI Memory Write and Invalidate
command ... enabled (in part) under Linux by pci_set_mwi().
However, very few Linux drivers use that routine. Given
that it can lead to improved performance, and that devices
don't have to implement that enable bit, I'm curious what
the story is...
- Just laziness or lack-of-education on the part of
- Iffy upport in motherboard chipsets or CPUs? If so,
- Flakey support in PCI devices, so that enabling it
leads to trouble?
- Something else?
- Combination of all the above?
Briefly, MWI can avoid some cache flushes, thereby reducing
memory bus contention. It can also enable longer PCI bursts
(since the dma master won't stop writing mid-cacheline).
And calling pci_set_mwi() makes sure that the device knows
the correct cache line size, which can make Memory Read
Multiple (and Memory Read Line) commands work better (also
with longer PCI bursts) by hinting to bridges when prefetch
would be a Fine Thing ... likewise reducing memory bus
contention. Those benefits can happen even if the hardware
doesn't support MWI; on my systems I noticed that the
cacheline size is always set too small by default, which
seems like a PCI initialization bug.
So what's the story ... is there some reason Linux isn't
trying to enable such PCI features more often? And why
it doesn't set the cacheline size correctly by default?
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This archive was generated by hypermail 2b29 : Thu Jan 23 2003 - 22:00:24 EST