> I suppose the potential for broken PCI devices is exactly why MWI
> isn't automatically enabled when DMA mastering is enabled, though
> I don't understand why the cacheline size doesn't get fixed then
> (unless it's that same issue). Devices can use the cacheline size
> to get better Memory Read Line/Read Multiple" throughput; setting
> it shouldn't be tied exclusively to enabling MWI.
There are a number of cases where we cant enable MWI either because
the PCI card doesnt support the CPU cacheline size or we have to set the
PCI card cacheline size to something smaller due to various bugs.
eg I understand earlier versions of the e100 dont support a 128 byte
cacheline (and the top bits are read only so setting it up for 128 bytes
will result in it it being set to 0). Not good for read multiple/line
and even worse if we decide to enable MWI :)
Anton
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This archive was generated by hypermail 2b29 : Fri Jan 31 2003 - 22:00:24 EST