> I suspect the ESR is a red herring. The problem is that the kernel
> assumes that the boot CPU is always CPU#0, and it also misprograms the
> boot CPU's APIC.
>
> What kind of SMP box is it (Intel/AMD)?
The boot cpu *is* always CPU#0. It may not be physical apicid 0, but that
matters not. as long as the mpstables are correct. And we should bug out if
it's not (which is pretty stupid anyway ... we know what the boot cpu ID
is, we should just warn). This is how I fixed it for kexec:
diff -urpN -X /home/fletch/.diff.exclude virgin/arch/i386/kernel/smpboot.c
nonzero_apicid/arch/i386/kernel/smpboot.c
--- virgin/arch/i386/kernel/smpboot.c Sat Feb 15 16:11:40 2003
+++ nonzero_apicid/arch/i386/kernel/smpboot.c Wed Feb 26 13:02:10 2003
@@ -951,6 +951,7 @@ static void __init smp_boot_cpus(unsigne
print_cpu_info(&cpu_data[0]);
boot_cpu_logical_apicid = logical_smp_processor_id();
+ boot_cpu_physical_apicid = hard_smp_processor_id();
current_thread_info()->cpu = 0;
smp_tune_scheduling();
-
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This archive was generated by hypermail 2b29 : Fri Feb 28 2003 - 22:00:39 EST