On Thu, Apr 03, 2003 at 12:33:59PM +0900, ISHIKAWA Mutsumi wrote:
> I've checked Intel E7205 and E7505 spec sheets. But I can not find
> why we should use device #1 (virtual agp bridge) instaed of device
> #0 (MCH).
Look at agp_3_0_node_enable()
In particular, the part that does a pci read of PCI_SECONDARY_BUS.
device #1 (AGP bridge) has 1:0.0 (AGP graphic card) as its secondary
bus here. Device #0 (Host bridge) doesn't have anything as a secondary
bus, so it can't mate the card with the bridge. So i7x05 jumps through
hoops using the wrong device in its agp_bridge->dev to get this right.
Its really fugly, and is against what every other gart driver is doing.
In my working tree (not yet pushed to bkbits) I've ripped out that
whole PCI_SECONDARY_BUS thing and replaced it with a simple bus scan
that looks for 2 devices that are AGP host and AGP target and pairs
them unconditionally.
This will probably break if ever someone does a >1 AGP Slot motherboard
but with vendors preffering to just dual-head AGP cards, and with PCI Express
in the pipeline, it's questionable whether or not we'll see them.
I've heard from one vendor who says they're interested in doing such a
board. If it ever sees light of day, it's worth worrying about,
(and this system sounds so niche I doubt it'd ever be mainstream anyway).
> I rewrite E7x05 agpgart driver to use device #0. It
> works fine for me (I tested it on E7505 motherboard with AGPx4
> card and AGPx8 card). To use MCH registers (on device #0) is generic
> way for Intel agpgart driver, so the driver can merge into intel-agp.c
> easyly.
I don't mind either way. If Matt wants to keep this as a seperate
subdriver I'll keep it as it is. If he's ok with the merge, I'll
apply your changes. The only questionable bit is the increase in
size of the respective modules by a few KB.
Thanks for your work..
Dave
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This archive was generated by hypermail 2b29 : Mon Apr 07 2003 - 22:00:19 EST