On Wed, Apr 16, 2003 at 05:04:27PM +0200, Andi Kleen wrote:
> On Wed, Apr 16, 2003 at 04:55:32PM +0200, Matthew Wilcox wrote:
> > On Wed, Apr 16, 2003 at 04:43:12PM +0200, Andi Kleen wrote:
> > > On sparc64. But is that true too for all other 64bit architectures supported?
> > >
> > > e.g. How about PA-RISC? (always seems to do things differently)
> >
> > As you know our only two atomic ops are load-and-clear 32-bit quantity and
> > load-and-clear 64-bit quantity. so we take one of the hashed spinlocks ..
>
> Sure, but you use a 64bit read/store in set_bit/clear_bit etc., right?
err.. so what? Once we've got the spinlock, other writers are blocked
and readers can either see the state before or the state after (stores
are atomic on PA)
> If yes then you can't use this unless you rewrite them to use 32bit store
> - otherwise it will conflict with the atomic_t counter in the 64bit slot
> which is not protected.
> I think my current patch is fine for you - you can still optimize it
> this way, but it should already work. Jakub's version would break though.
Jacob's would break if we hashed to different spinlocks. But we don't, we
shift right by 8, so we get the same spinlock for atomic things that are on
the same "cacheline" (i think PA cachelines are actually 64 or 128 bytes,
depending on model).
-- "It's not Hollywood. War is real, war is primarily not about defeat or victory, it is about death. I've seen thousands and thousands of dead bodies. Do you think I want to have an academic debate on this subject?" -- Robert Fisk - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Wed Apr 23 2003 - 22:00:18 EST