That's what I thought, which is why I suspected that the underlying problem
might be related to the scope and completeness of the hardware arbitration.
Specifically, if a PCI board is DMA'ing a block of data to main memory, how
is the operation of the direct-connect IDE device impacted? When most PCI
devices transfer data to main memory, don't they arbitrate the bus, become
master, and blast it accross in chunks? Doesn't onboard IDE (legacy?) use
the DMA controller (8237 derivate I gues) to transfer?
On Wednesday 23 April 2003 06:11 pm, Alan Cox wrote:
> On Mer, 2003-04-23 at 23:13, joe briggs wrote:
> > Is this true??? Does onboard IDE controllers appear and work the same way
> > as IDE or PCI controllers with respect to IRQ, DMA, and memory access?
>
> They appear to. Most of them nowdays are wired directly to the
> north/southbridge link for performance.
>
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-- Joe Briggs Briggs Media Systems 105 Burnsen Ave. Manchester NH 01304 USA TEL/FAX 603-232-3115 MOBILE 603-493-2386 www.briggsmedia.com - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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