On Maw, 2003-05-06 at 11:41, Zwane Mwaikambo wrote:
> > For anything where you get pairs of close IRQ's
>
> Shouldn't this also be observed more easily on P4/xAPIC since you can have
> a pending vector in the IRR and ISR whilst the core processes one.
I don't know enough about the pending vector stuff. For the older APIC the
IRQ's go via a suprisingly slow seperate APIC bus (4 wire if I remember
rightly).
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