Re: [PATCH] remove IO APIC newline

From: Diego Calleja García (diegocg@teleline.es)
Date: Fri Jun 27 2003 - 13:57:42 EST

On Fri, 27 Jun 2003 14:41:11 -0400
Jeff Garzik <jgarzik@pobox.com> wrote:

> Personally the IO-APIC gunk is gunk that should be hidden behind
> DPRINTK... SMP machines spam dmesg _way_ too much. Especially once you
> get above 4 processors.

I did a patch wich makes dmesg output of SMP machines better. Well, it doesn't
adds or removes any line; but it says "CPUX:". The patch ugly, basically
it adds smp_processor_id() output in every printk i found. I did it because
IMHO messages like "Intel machine check architecture supported" in a SMP machine
are ugly. I'd found it specially nice for big SMP boxes because this does dmesg
easily grep'able.

-Initializing CPU#0
+CPU0: Initializing
[...]
-Calibrating delay loop... 1602.35 BogoMIPS
+CPU0: Calibrating delay loop... 1602.35 BogoMIPS
[...]
-CPU: L1 I cache: 16K, L1 D cache: 16K
-CPU: L2 cache: 256K
-CPU: After generic, caps: 0383fbff 00000000 00000000 00000040
-Intel machine check architecture supported.
-Intel machine check reporting enabled on CPU#0.
-Enabling fast FPU save and restore... done.
-Enabling unmasked SIMD FPU exception support... done.
-Checking 'hlt' instruction... OK.
+CPU0: L1 I cache: 16K, L1 D cache: 16K
+CPU0: L2 cache: 256K
+CPU0: After generic, caps: 0383fbff 00000000 00000000 00000040
+CPU0: Intel machine check architecture supported.
+CPU0: Intel machine check reporting enabled.
+CPU0: Enabling fast FPU save and restore... done.
+CPU0: Enabling unmasked SIMD FPU exception support... done.
+CPU0: Checking 'hlt' instruction... OK.
[...]
-enabled ExtINT on CPU#0
-ESR value before enabling vector: 00000000
-ESR value after enabling vector: 00000000
+CPU0: enabled ExtINT.
+CPU0: ESR value before enabling vector: 00000000
+CPU0: ESR value after enabling vector: 00000000
[...]
-Initializing CPU#1
-masked ExtINT on CPU#1
-ESR value before enabling vector: 00000000
-ESR value after enabling vector: 00000000
-Calibrating delay loop... 1605.63 BogoMIPS
-CPU: L1 I cache: 16K, L1 D cache: 16K
-CPU: L2 cache: 256K
-CPU: After generic, caps: 0383fbff 00000000 00000000 00000040
-Intel machine check architecture supported.
-Intel machine check reporting enabled on CPU#1.
+CPU1: Initializing
+CPU1: masked ExtINT.
+CPU1: ESR value before enabling vector: 00000000
+CPU1: ESR value after enabling vector: 00000000
+CPU1: Calibrating delay loop... 1605.63 BogoMIPS
+CPU1: L1 I cache: 16K, L1 D cache: 16K
+CPU1: L2 cache: 256K
+CPU1: After generic, caps: 0383fbff 00000000 00000000 00000040
+CPU1: Intel machine check architecture supported.
+CPU1: Intel machine check reporting enabled.
[...]
-Enabling SEP on CPU 1
-Enabling SEP on CPU 0
+CPU1: Enabling SEP
+CPU0: Enabling SEP


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This archive was generated by hypermail 2b29 : Mon Jun 30 2003 - 22:00:27 EST