Re: 2.6.0-test3-mm1: scheduling while atomic (ext3?)

[Alan Cox]

On Mer, 2003-08-13 at 17:39, Dave Jones wrote:
>  > several instructions later added (including prefetch). The later Cyrix
>  > also has a couple of the additional ones but not prefetch.

Ok I got this crossed - the Cyrix/AMD thing was the extended MMX stuff,
they both did 3Dnow! but the Jalapeno old style Cyrix CPU with 3dnow was
canned. Ok so there is a different reason why my Cyrix crashes on boot
with 2.6test. Andi is right that 3Dnow safely implies prefetch. My docs
list it as part of extended MMX not 3dnow although the Cyrix seems to
not posess the instruction anyway.

So 3dnow == prefetch/prefetchw is ok but not useful on K6.

> Which Cyrixen are you talking about ?
> C3's up to and including Ezra-T should DTRT when it comes to
> 3dnow prefetch instruction, and pre-VIA Cyrixen didn't have 3dnow
> at all iirc.

pre VIA Cyrixen have MMX and CXMMX. The CPU also set bit 31 but doesn't
have 3dnow (which fooled me but the kernel does know about). C3's seem
to have prefetch/prefetchw (but not prefetchnta). I don't have a nemeiah
but I assume Nemeiah has prefetchnta too ?


I've tried building a summary list. Additional contributions welcomed

MMX:  Pentium (later only), Cyrix MediaGX (later only), Cyrix 6x86/MII
      Intel PII/PIII/PIV, AMD K6/Athlon/Opteron, VIA Cyrix III, VIA C3
CXMMX: Extended MMX - Cyrix MII/AMD K6(II+ ?)/K7/Opteron
3DNOW: AMD K6-II/III(not original K6),K7/,Opteron, VIA Cyrix III, 
VIA C3 (pre Nemiah only ??)
"Enhanced" 3DNow: Athlon Tbird
SSE: Intel PII, PIII, Athlon (XP, Duron >=1Gz only)
SSE2: Pentium IV
 
So the prefetch fallback is needed for pre Nemiah C3, Duron < 1Ghz and
pre T-Bird Athlon if my table is right.


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