Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Roland Dreier]

    Matt> PPC440GX, non cache coherent, L1 icache is VTPI, L1 dcache
    Matt> is PTPI

    Jamie> The cache looks very coherent to me.

Matt (like me) is probably just used to thinking of the IBM PPC 440
chips as non-coherent because they are not cache coherent with respect
to external bus masters (eg they don't snoop the PCI bus).  Of course,
this is a different type of coherency from what you are measuring.

 - Roland
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