Re: [PATCH] Athlon Prefetch workaround for 2.6.0test6

[Dave Jones]

On Mon, Sep 29, 2003 at 09:02:39PM +0000, bill davidsen wrote:
 > In article <20030929125629.GA1746@averell>, Andi Kleen  <ak@xxxxxx> wrote:
 > 
 > | It removes the previous dumb in kernel workaround for this and shrinks the 
 > | kernel by >10k.
 > | 
 > | Small behaviour change is that a SIGBUS fault for a *_user access will
 > | cause an EFAULT now, no SIGBUS.
 > | 
 > | This version addresses all criticism that I got for previous versions.
 > | 
 > | - Only checks on AMD K7+ CPUs. 
 > | - Computes linear address for VM86 mode or code segments
 > | with non zero base.
 > | - Some cleanup
 > | - No pointer comparisons
 > | - More comments
 > 
 > I have to try this on a P4 and K7, but WRT "Only checks on AMD K7+ CPUs"
 > I hope you meant "only generates code if AMD CPU is target" and not that
 > the code size penalty is still there for CPUs which don't need it.

NO NO NO NO NO.
This *has* to be there on a P4 kernel too, as we can now boot those on a K7 too.
The 'code size penalty' you talk about is in the region of a few hundred
bytes. Much less than a page. There are far more obvious bloat candidates.

		Dave

-- 
 Dave Jones     http://www.codemonkey.org.uk
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