Re: [Patch] dma_sync_to_device

[David S. Miller]

On Wed, 11 Feb 2004 11:18:00 -0700
Matt Porter <mporter@xxxxxxxxxxxxxxxxxxx> wrote:

> Sure, other non cache coherent arch's that I'm aware of (PPC, ARM, etc.)
> already implement the least expensive cache operations based on the
> direction parameter in pci_dma_sync_single(). On PPC, we do the right
> thing based on each of three valid directions, I don't yet see what
> additional information pci_dma_sync_to_device_single() provides. 

There are two points in time where you want to sync:

1) Right after the device has done a DMA transaction, and the cpu
   wishes to read/write the datum.

2) Right after the cpu has read/write the datum, and we like to let the
   device DMA to/from the thing again.

That is the distinction provided by the two interfaces.

Consider something like MIPS, cache flushes needed for both of the above
operations:

1) pci_map_single(), device DMA's from the buffer.

2) pci_dma_sync_single().  Cpu writes some new command or
   status flag into the buffer.

3) pci_dma_sync_to_device_single(), now device is asked to DMA from the buffer
   again.

Cache flushes are needed on MIPS for both step #2 and #3, and different kinds of
flushes in fact.

Do you understand the need for this now?
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