Re: PAT support

[Eric W. Biederman]

Manfred Spraul <manfred@xxxxxxxxxxxxxxxx> writes:

> Hi Terence,
> 
> in your patch, you write
> +/* Here is the PAT's default layout on ia32 cpus when we are done.
> + * PAT0: Write Back
> + * PAT1: Write Combine
> + * PAT2: Uncached
> + * PAT3: Uncacheable
> + * PAT4: Write Through
> + * PAT5: Write Protect
> + * PAT6: Uncached
> + * PAT7: Uncacheable
> 
> Is that layout possible?
> There is an errata in the B2 and C1 stepping of the Pentium 4 cpus that results
> in incorrect PAT numbers: the highest bit is ignored by the CPU under some
> circumstances. There's a similar errata (E27) that affects all Pentium 3 cpus:
> The highest bit is always ignored.
> I think we need a fallback to 4 PAT entries.

Write Through and Write Protect are essentially useless.  So that should
be easy to do.

Eric
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