Re: 2.6.6-mm5

[Eric W. Biederman]

Roland Dreier <roland@xxxxxxxxxxx> writes:

>     Eric> If no hardware actually cared or someone could show me that
>     Eric> you can't generate a 64bit memory I/O cycle on the PCI bus
>     Eric> that would be interesting.  I have seen several drivers that
>     Eric> care.  Later today I intend to look at my pci docs and
>     Eric> confirm that 64bit I/O cycles do exist on the bus, even in
>     Eric> 32bit slots.  PCI bus traffic is packet based so I would be
>     Eric> strongly surprised if 64bit cycles did not exist.
> 
> Hang on -- how could you generate a 64-bit cycle on a 32-bit PCI bus?
> By definition a 32-bit PCI bus can only transfer 32 bits per cycle.
> 
> PCI Express traffic is packet based but parallel PCI definitely is not.

But parallel PCI is transaction based, which largely gives the same
effect as being packet based.  And you can have man data cycles for
every address cycle.  What I am not yet clear are the transaction splitting
rules.  My outstanding questions that I really need to track down are:

- Must a 64bit memory write transaction have the same effect as 2
  32bit write transactions?   

- Must a 64bit read transaction have the same effect as 2 32bit
  read transactions?

If true then it is impossible to implement the corresponding 64bit
atomic transaction on the PCI bus, and locks are required for
everyone's code.

The same questions can be asked of PCI-Express.

As soon as I managed to dig a copy of the protocol specifications
I will see if I can answer those questions.  

Eric

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