Re: DMA API issues

[James Bottomley]

On Sun, 2004-06-20 at 10:50, Ian Molton wrote:
> Those two statements are contradictory. clearly the iseries cant use the
> DMA API *now* so I dont see how that makes any difference. We're talking
> about adding propper support for *addresssable* memory mapped devices
> with limited size DMA-able windows to the DMA API, not adding support
> for a whole new weird way of talking to devices. These devices work the
> same way as all the other devices that use the DMA API but are simply
> restricted in the range of addresses they can DMA from. they require no
> special 'accessors'.
> 
> iseries cant work the usual way now and wont with these modifications -
> so nothing is made worse.

OK, let's try and make this as simple as I know how.  The system looks
like this


       +-----+
       | CPU |
       +--+--+
          |
    <-----+-----+----------------------+-----> Central Bus
                |                      |
          +-----+------+        +------+-----+
          |   Memory   |        |    I/O     |
          | Controller |        | Controller |
          +-----+------+        +------+-----+
                |                      |
            +---+-----+             +--+---+    +--------+
            | Memory  |             | OHCI |----| Memory |
            +---------+             +------+    +--------+

In order to access this OHCI memory, both the I/O controller and the
OHCI have to respond to the memory access cycles, rather than the memory
controller.  This is why such memory is termed "bus remote".

Even though ARM can programm the I/O controller and the OHCI device to
access this memory as though it were behind the memory controller (i.e.
using normal CPU memory cycles), you'll find that even on ARM there's
probably special page table trickery involved (probably to do with cache
coherency issues).  Next, you'll find that no other device can see this
memory without some type of i2o support, so it can't be the target of a
DMA transaction. So even on ARM, you can't treat it as "normal" memory.

On iSeries, the I/O controller sits behind the hypervisor and can't be
the target of normal memory cycles, that's why the CPU can't address
this bus remote memory normally. As I've explained.

The DMA API is about allowing devices to transact directly with memory
behind the memory controller, it's an API that essentially allows the
I/O controller and memory controller to communicate without CPU
intervention.  This is still possible through the hypervisor, so the
iSeries currently fully implements the DMA API.

James


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