RE: [PATCH] [broken?] Add MSI support to e1000

[Nguyen, Tom L]

On Monday, August 23, 2004 Roland Dreier wrote:
>It seems e1000 does not support the per-vector masking feature of MSI
>(see full PCI header dump below).

You're right that e1000 hardware does not support the per-vector masking
feature.

>However if I understand the x86 APIC properly, even without masking,
>edge-triggered MSI interrupts should work OK.  As I understand it,
>when the interrupt is dispatched, its bit is moved from the IRR to the
>ISR.  If the same interrupt is received while the interrupt handler is
>running, its bit will be set again in the IRR and it will be
>dispatched again as soon as the handler exits.

Agree. The question is that how many egde-triggered MSI with the same 
vector are generated by e1000 hardware when its service handler is 
still running.

>It seems this should work OK for e1000 -- the chip should not generate
>another MSI until the driver reads the ICR in the interrupt handler,
>although it might generate an interrupt immediately afterward (while
>the interrupt handler is still running).

I do not know much about e1000 hardware. I leave it to Ganesh for an
answer.

Thanks,
Long 
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