RE: [PATCH] pci-mmconfig fix for 2.6.9

From: Michael Chan
Date: Sat Nov 13 2004 - 11:24:20 EST

> If I got the discussion so far correctly then the PCI-SGI spec does not
> guarantee that there is no posting, but you know that the chipset
> you are using right now doesn't do it.

Yes, that's my understanding of the spec. Grant Grundler does not agree and thinks that non-posting is the only compliant implementation. I wish he was right as it would be the easiest to deal with. We contacted Intel about the out-of-spec readl when writing to the PMCSR to change power state as they were the original author of the mmconfig code. Their solution was to remove the readl after confirming that mmconfig was non-posted on their chipsets.

> The problem with the explanation is that there will be very soon
> chipsets not from Intel that also implement PCI-Express. And also
> even systems with non Intel CPUs that also do PCI-Express and
> mmconfig.

I agree with you. Having the readl would be the safest and the most conservative approach. But it is out-of-spec to have a readl immediately following writel to the PMCSR when power state is changed. So should we have a relaxed version of pci_write_config_* with no flushing read for programming the PMCSR?


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