Re: [PATCH 0/3] NUMA boot hash allocation interleaving

From: Eric Dumazet
Date: Wed Dec 15 2004 - 02:43:23 EST

Andi Kleen wrote:

I actually considered implementing it for x86-64 some time ago
for the modules, but then I never bothered. On AMD systems
I actually prefer to use small pages here. The reason is that
Opteron has a separated large and small pages TLB and the small
pages TLB is much bigger. When someone else uses huge TLB pages too (user space or kernel direct mapping) then it's actually
a good idea to use small pages.


I actually use dual Opterons systems, with very large route cache hashes and tcp hashes. (rhash_entries=524288 thash_entries=524288), and a Hugetlb aware user space programs.

x86info tells me (maybe wrongly)

Family: 15 Model: 5 Stepping: 8
CPU Model : Opteron
Instruction TLB: Fully associative. 32 entries.
Data TLB: Fully associative. 32 entries.

and /proc/cpuinfo tells me :
model name : AMD Opteron(tm) Processor 248
TLB size : 1088 4K pages

My questions are :

1) Are the route cache and tcp hashes use big pages (2MB) on 2.6.5/2.6.9 x86_64 kernels.
2) What are the exact number of data TLB entries (for small pages and huge ones) for opterons ?
3) All networks interrupts are handled by CPU0. Should we really use NUMA interleaved memory for hashes in this case ?

Thank you
Eric Dumazet
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