Re: Patch: ATI Xilleon port 2/11 net/e100 Memory barriers andwrite flushing

[Arjan van de Ven]

On Wed, 2005-10-19 at 22:54 -0700, David Daney wrote:
> This is the second part of my Xilleon port.
> 
> I am sending the full set of patches to linux-mips@xxxxxxxxxxxxxx
> which is archived at: http://www.linux-mips.org/archives/
> 
> Only the patches that touch generic parts of the kernel are coming
> here.
> 
> The Xilleon (32bit MIPS SOC) has a write back buffer that seems to
> operate on the pci bus and does not get flushed before a read.  The
> result is that a memory barrier must be done before a read intended to
> flush PCI writes.

this is broken hardware; the real solution is to put that wmb() into the
readl() function, as opposed to patching half the kernel for this!

And the second problem seems to be an reodering, which is also not quite
allowed. That also needs fixing, probably in the writel/writeb() macros.


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