Re: [PATCHSET] block: fix PIO cache coherency bug

[David S. Miller]

From: James Bottomley <James.Bottomley@xxxxxxxxxxxx>
Date: Fri, 13 Jan 2006 16:38:49 -0600

> Could someone explain (or give a reference to) the actual problem?  If
> it's a cache coherency issue it should show up with VIPT arhictectures
> as well as VIVT ones ... I have access to parisc systems (with SCSI),
> which are VIPT.

Not true, VIPT caches participate in cache coherency transactions
with the PCI host controller (and thus the PCI device), whereas
VIVT caches do not.

It does make a big difference, it's very hard to share datastructures
with a device concurrently accessing them (what we call PCI consistent
DMA mappings) on a VIVT cache.
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