Re: [PATCH 2.6.15.3] alpha/pci: set cache line size for cards ignored by SRM

[Gabriele Gorla]

> On Tue, Feb 07, 2006 at 02:54:43PM -0800, Gabriele Gorla wrote:
>> Set the cache line size in the PCI configuration space to a reasonable
>> value. SRM does not seem to set this register for the PCI cards that it
>> does not recognize. This makes drivers that expect cache line size to be
>> set by the card bios work on alpha.
>
> I don't see such drivers in the mainline.
that sata_sil driver uses the cache line register to tune some FIFO
registers.

> Anyhow, the PCI_CACHE_LINE_SIZE setting is critical only for devices
> that do memory-write-invalidate. In this case a driver must call
> pci_set_mwi() which takes care of PCI_CACHE_LINE_SIZE.
sata_sil is not capable of MWI so it does not call pci_set_mwi()

I looked at the config space on a PC and alpha before the sata_sil driver
is loaded and it is different.
I suspect on the PC the system bios or the card bios set up this register
during post.

The sata_sil driver may not be doing the correct thing, however it seems
reasonable to assume that the device is configured properly (by system
bios or kernel fixup) before the driver init code executes.
This seems the same behavior of ppc and sparc64 pci code as well.

thanks,
GG

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