Re: [PATCH] Define wc_wmb, a write barrier for PCI write combining

[Jesse Barnes]

On Tuesday, February 28, 2006 9:02 am, Roland Dreier wrote:
>     Jes> Not quite correct as far as I understand it. mmiowb() is
>     Jes> supposed to guarantee that writes to MMIO space have
>     Jes> completed before continuing.  That of course covers the
>     Jes> multi-CPU case, but it should also cover the write-combining
>     Jes> case.
>
> I don't believe this is correct.  mmiowb() does not guarantee that
> writes have completed -- they may still be pending in a buffer in a
> bridge somewhere.  The _only_ effect of mmiowb() is to make sure that
> writes which have been ordered between CPUs using some other mechanism
> (i.e. a lock) are properly ordered by the rest of the system.  This
> only has an effect systems like very large ia64 systems, where (as I
> understand it), writes can pass each other on the way to the PCI bus.
> In fact, mmiowb() is a NOP on essentially every architecture.

I think it could be implemented meaningfully on ppc64, mips64, and 
perhaps some parisc systems, but I don't think their respective 
maintainers have gotten around to that yet.

Anyway, it looks like the write combine ordering Bryan is talking about 
really is a distinct semantic.  Not sure if it's possible (or desirable) 
to overload an existing barrier op to include the semantics he wants.

Jesse
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