RE: Problems with EDAC coexisting with BIOS

[Ong, Soo Keong]

There are 4 occasions (that I aware of) during the OS times that could
possibly trigger SMI

1. Before OS USB driver disconnect SMI from USB controller
2. ACPI driver call software SMI once
3. SpeedStep using ACPI interface
4. Error (connected to SMI) happens

I know there are always ways to improve BIOS. Allow me to look at the OS
first so that OS can be robust enough to handle different
implementations.

1 and 2 will be gone early in booting. 3 could be handled appropriately
by OS because OS knows when SpeedStep ACPI interface is called and is
done. 4 will be gone after error interrupt re-connection done by OS
after phase 1 and 2.

I am not the one who prefer error handling stay in BIOS, but many people
have different opinion from me.

I logout now.

-----Original Message-----
From: Alan Cox [mailto:alan@xxxxxxxxxxxxxxxxxxx] 
Sent: Monday, April 24, 2006 10:30 PM
To: Ong, Soo Keong
Cc: Gross, Mark; bluesmoke-devel@xxxxxxxxxxxxxxxxxxxxx; LKML; Carbonari,
Steven; Wang, Zhenyu Z
Subject: RE: Problems with EDAC coexisting with BIOS

On Llu, 2006-04-24 at 22:15 +0800, Ong, Soo Keong wrote:
> To me, periodical is not a good design for error handling, it wastes
> transaction bandwidth that should be used for other more productive
> purposes.

The periodical choice is mostly down to the brain damaged choice of NMI
as the viable alternative, which is as good as 'not usable'

> It is more appropriate to have single handler, either OS or BIOS.

Agreed but then the BIOS must provide that service to the OS reliably
and efficiently so that users can build that service into their system
wide error management and control processes.

> In general, the errors handler connect the errors to the interrupt or
> interrutps. The handler should undhide (if it s hideable) the error
> controller and read its registers upon interrupt, then carry out
> appropriate actions to handle the erros.

Actually I am dubious that the error handler can do that. If the OS
kernel just issued the first half of a config cycle what occurs when the
SMI tries to play with PCI config space ? 
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