Re: Segfault on the i386 enter instruction
From: Andi Kleen
Date: Tue May 16 2006 - 05:36:40 EST
On Tuesday 16 May 2006 04:29, Chuck Ebbert wrote:
> In-Reply-To: <44676F42.7080907@xxxxxxxx>
> On Sun, 14 May 2006 21:56:18 +0400, Stas Sergeev wrote:
> > Andi Kleen wrote:
> > > Handling it like you expect would require to disassemble
> > > the function in the page fault handler and it's probably not
> > > worth doing that for this weird case.
> > Just wondering, is this case really that weird?
> > In fact, the check against %esp that the kernel
> > does, looks strange. I realize that it can catch a
> > (very rare) user-space bug of accessing below %esp, but
> > other than that it looks redundant (IMHO) and as soon as
> > it triggers the false-positives, what is it really good for?
> I can't get a SIGSEGV on any native i386 kernel, not even when
> running on AMD64. It only happens on native x86_64 kernels.
I reproduced the original SIGSEGV on several i386 kernels.
> Intel says nothing about a write check. Is that a mistake in the manual
> or is that something only AMD64 does, and then only in long mode?
In 98+% of all cases when Intel and AMD documentation differ
in subtle detail it's a documentation bug.
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