Re: Support for TI FlashMedia (pci id 104c:8033, 104c:803b) flash card readers

[Alex Dubov]

--- Pierre Ossman <drzeus-list@xxxxxxxxx> wrote:

> Russell King wrote:
> > It's really the bus we care about at this stage, since the errors we
> > receive are along the lines of "the card reported that the last data
> > block had a CRC error", "we encountered an underrun condition during
> > the last data block", or "the card didn't request data before we
> > timed out", etc.
> >
> > Basically, the transfer of the next block confirms that the previous
> > block was successfully received by the card.
> >
> >   
> 
> Ehm... Now I'm a bit confused. At the point of a bus error, there
> difference between the data sent to the bus and the data successfully
> received by the card should amount to one block (as the last block got
> NACK:ed for whatever reason). If we expect host drivers to report the
> bytes sent to the bus, we need to subtract one block from the value
> reported to the block layer.
> 
> Rgds
> Pierre
> 
If I understand correctly, there should be two different ways to report bytes_xfered:
1. for read operations, the current block/byte counter reporting is sufficient
2. for write operation, error-less BUSY assert/de-assert pairs shall be counted instead
Currently I only look at the last BUSY de-assert to verify that command is completed successfully.
As mmc_block always issues single block writes it is sufficient. If this will ever change, more
sophisticated scheme can be devised.


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