Re: question regarding cacheline size
From: Arjan van de Ven
Date: Thu Sep 07 2006 - 08:30:55 EST
>
> So I think we should redo the PCI subsystem to set cacheline size during
> the buswalk rather than waiting for drivers to ask for it to be set.
... while allowing for quirks for devices that go puke when this
register gets written ;)
(afaik there are a few)
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