Re: question regarding cacheline size

[Jeff Garzik]

Grant Grundler wrote:
> hrm...if the driver can put a safe value in cachelinesize register
> and NOT enable MWI, I can imagine a significant performance boost
> if the device can use MRM or MRL. But IMHO it's up to the driver
> writers (or other contributors) to figure that out.

Yes.


> Current API (pci_set_mwi()) ties enabling MRM/MRL with enabling MWI
> and I don't see a really good reason for that. Only the converse
> is true - enabling MWI requires setting cachelinesize.

Correct, that's why it was done that way, when I wrote the API. 
Enabling MWI required making sure the BIOS configured our CLS for us, 
which was often not the case.  No reason why we can't do a

	pdev->set_cls = 1;
	rc = pci_enable_device(pdev);

or

	rc = pci_set_cacheline_size(pdev);

Regards,

	Jeff



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