Re: Uses for memory barriers

[Paul E. McKenney]

On Tue, Sep 19, 2006 at 04:38:19PM -0400, Alan Stern wrote:
> On Tue, 19 Sep 2006, Paul E. McKenney wrote:
> 
> > > Maybe I'm missing something. But if the same CPU loads the value
> > > before the store becomes visible to cache coherency, it might see
> > > the value out of any order any of the other CPUs sees.
> > 
> > Agreed.  But the CPUs would have to refer to a fine-grained synchronized
> > timebase or to some other variable in order to detect the fact that there
> > were in fact multiple different values for the same variable at the same
> > time (held in the different store queues).
> 
> Even that wouldn't be illegal.  No one ever said that any particular write 
> becomes visible to all CPUs at the same time.

Agreed.  But this would be outside of the cache-coherence protocol.

That said, cross-CPU timing measurements have been very helpful to
me in the past when messing with memory ordering.  Spooky to be able
to prove that a single variable really does have multiple values at
a single point in time, from the perspectives of different CPUs!  ;-)

> > If the CPUs looked only at that one single variable being stored to,
> > could they have inconsistent opinions about the order of values that
> > this single variable took on?  My belief is that they could not.
> 
> Yes, I think this must be right.  If a store is hung up in a CPU's store 
> buffer, it will mask later stores by other CPUs (i.e., prevent them from 
> becoming visible to the CPU that owns the store buffer).  Hence all stores 
> that _do_ become visible will appear in a consistent order.
> 
> But my knowledge of outlandish hardware is extremely limited, so don't 
> take my word as gospel.

All the hardware that I have had intimate knowledge of has adhered to
this constraint.

							Thanx, Paul
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