Re: [PATCH 1/3] Fix COW D-cache aliasing on fork

From: Ralf Baechle
Date: Fri Oct 20 2006 - 20:06:32 EST

On Fri, Oct 20, 2006 at 04:28:37PM -0700, Linus Torvalds wrote:

> > > My understanding is that this works because in Ralf's original patch
> > > (which is the context in which he is removing the flush_cache_mm()
> > > call), he uses kmap()/kunmap() to map the page(s) being accessed at a
> > > kernel virtual address which will fall into the same cache color as
> > > the user virtual address --> no alias problems.
> > >
> > > Since he does this for every page touched on the kernel side during
> > > dup_mmap(), the existing flush_cache_mm() call in dup_mmap() does in
> > > fact become redundant.
> >
> > Correct.
> >
> > It means no cache flush operation to deal with aliases at all left in
> > fork and COW code.
> Umm. That would seem to only happen to work for a direct-mapped virtually
> indexed cache where the index is taken purely from the virtual address,
> and there are no "process context" bits in the virtually indexed D$.

No MIPS processor has something like that. See below.

> The moment there are process context bits involved, afaik you absolutely
> _need_ to flush, because otherwise the other process will never pick up
> the dirty state (which it would need to reload from memory).


> That said, maybe nobody does that. Virtual caches are a total braindamage
> in the first place, so hopefully they have limited use.

On MIPS we never had pure virtual caches. The major variants in existence

o D-cache PIPT, I-cache PIPT
o PIVT (no typo!)
Only the R6000 has this and it's not supported by Linux.
o D-cache VIPT, I-cache VIPT
This is by far the most common on any MIPS designed since '91.
A variant of these caches has hardware logic to detect cache aliases and
fix them automatically and therefore is equivalent to PIPT even though
they are not implemented as PIPT. And obviously the alias replay of the
pipe will cost a few cycles. The R10000 family of SGI belongs into this
class and the 24K/34K family of synthesizable cores by MIPS Technologies
have this as a synthesis option.
Another variant throws virtual coherency exceptions as I've explained in
another thread.
o D-cache PIPT, I-cache VIVT with additional address space tags.
o Cacheless. Not usually running Linux but heck, it's working anyway.

Be sure I'm sending a CPU designers a strong message about aliases. And I
think they're slowly getting the message that kernel hackers like to poke
needles into voodoo dolls for aliases ;-)

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