Re: [PATCH] fix atl1 braino

[Chuck Ebbert]

Al Viro wrote:
> Spot the bug...
> 
> Signed-off-by: Al Viro <viro@xxxxxxxxxxxxxxxxxx>
> ---
> 
> diff --git a/drivers/net/atl1/atl1_hw.c b/drivers/net/atl1/atl1_hw.c
> index 08b2d78..e28707a 100644
> --- a/drivers/net/atl1/atl1_hw.c
> +++ b/drivers/net/atl1/atl1_hw.c
> @@ -357,7 +357,7 @@ void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
>  	 */
>  	hash_reg = (hash_value >> 31) & 0x1;
>  	hash_bit = (hash_value >> 26) & 0x1F;
> -	mta = ioread32((hw + REG_RX_HASH_TABLE) + (hash_reg << 2));
> +	mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
>  	mta |= (1 << hash_bit);
>  	iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
>  }

The comment above is funny:

349 /*
350 * The HASH Table is a register array of 2 32-bit registers.
351 * It is treated like an array of 64 bits. We want to set
352 * bit BitArray[hash_value]. So we figure out what register
353 * the bit is in, read it, OR in the new bit, then write
354 * back the new value. The register is determined by the
355 * upper 7 bits of the hash value and the bit within that
356 * register are determined by the lower 5 bits of the value.

How can you use seven bits to choose between two registers?
And they're not using the lower 5 bits, but rather bits 30..26.

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