Re: [PATCH] [16/35] i386: Add an option for the VIA C7 which setsappropriate L1 cache

From: Jeff Garzik
Date: Sat Apr 28 2007 - 14:10:50 EST

Andi Kleen wrote:
From: Simon Arlott <simon@xxxxxxxxxx>

The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has
a cache line length of 64 according to This patch sets
gcc to -march=686 and select s the correct cache shift.

Signed-off-by: Simon Arlott <simon@xxxxxxxxxxx>
Signed-off-by: Andi Kleen <ak@xxxxxxx>
Cc: Andi Kleen <ak@xxxxxxx>
Cc: Dave Jones <davej@xxxxxxxxxxxxxxxxx>
Cc: Alan Cox <alan@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>

Has it been verified in the field that this CPU supports CMOV?


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