Re: Few interrupts with NO_HZ

From: Chris Snook
Date: Mon Aug 06 2007 - 10:35:47 EST


Jan Engelhardt wrote:
On Aug 6 2007 09:47, Chris Snook wrote:
this more of an informational question. So:
kernel version is 2.6.22.1 on i686
/proc/uptime 9917.81 9140.90 (2h45m)
/proc/cpuinfo:
CPU0
0: 282 IO-APIC-edge timer

this is kinda neat, I expected much more interrupts than just 282
since boot. What kernel code actually uses the irq0 timer?
If you don't have an HPET (and most single-processor systems do not)

This is an AMD Athlon with 'Thoroughbred' core; it does not seem to
have C-states at all (or: exactly one). It clearly is not idle all the
time, sometimes I run povray. (And 282 has not changed since the
morning.)


Jan

In that case, it's probably the early bootstrap code that runs before the TSC is calibrated. PIT sucks, but it sucks very reliably, so it's a good basis for calibrating the other timekeeping devices. Once you have something better set up, you don't need it anymore if you're not doing C-state transitions.

-- Chris
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