Re: question on odd APIC behavior

[Maciej W. Rozycki]

On Thu, 15 Nov 2007, Oliver Neukum wrote:

> >  Certainly.  One possibility is to have multiple processors marked as the 
> > destination, e.g. a logical delivery mode destination programmed with 
> > multiple bits set.
> 
> What would be the consequences?

 It depends on the exact setup and conditions.

> I am seeing an interrupt for an UHCI on #20 CPU1 also arriving on
> #19 CPU0, triggering the spurious interrupt detection.

 Well, if you see spurious interrupt detection triggered, then it is not a 
problem with the interrupt being delivered multiple times (that's handled 
silently by the interrupt dispatched), but likely the interrupt line being 
deasserted too late.  Does it happen frequently?  If your ERR counter in 
/proc/interrupts increments quite fast, then perhaps a driver does not 
handle interrupts well enough for your system.  Or there is noise on an 
interrupt line.

 You would have to provide more information to get more accurate feedback.

  Maciej
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