Re: [RT] MPIC edge sensitive issues with hardirq preemption

[Sergei Shtylyov]

Hello.

Anton Vorontsov wrote:

> But how this could be a bug in the PIC code? IMO this is a bug in the
> kernel/irq code, since it assumes that fasteoi PIC will retrigger masked
> edge sources... This isn't true for at least MPIC. To make this work for
> all fasteoi PICs, we should mask edge sensitive interrupts very very
> carefully.
>   

  I guess it assumed this based on 8259's behavior (not sure about I/O 
APIC).
  Hm, but the 8259 code never used "fasteoi" path for some obscure 
reason...

> jammed with the idea that MPIC irq type 0 is low level sensitive, but the
> true thing is that it is rising edge sensitive. (Ah, I know where I got
> confused, type 0 is active-low for ISA PICs).
>   

   You mean in the device tree?

> So in all my previous emails I was wrong when I was saying "mpic is
> programmed to low level sensitive". It was programmed for rising edge
> sensitive. An all my further reasonings were flawed because of this.
>   

  Gah.  I'm surprised how it could work at all then...

> Re-programming MPIC to high level sensitive also makes IDE work. But
> this doesn't mean that IRQ code is correct.
>   

  I wonder why. :-O
  Your ULi IDE is in native mode, so it should be generating a PCI 
interrupt -- which is *low* level sensitive.

MBR, Sergei


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