On Mon, Jun 30, 2008 at 03:42:47PM -0700, H. Peter Anvin wrote:Jeremy Fitzhardinge wrote:Maybe it really does require the far jump immediately after setting PE in cr0...I don't remember that, either.
Hm, I don't remember this paragraph being in vol 3a, section 8.9.1 before. Is it a recent addition?
Random failures can occur if other instructions exist between steps
3 and 4 above. Failures will be readily seen in some situations,
such as when instructions that reference memory are inserted between
steps 3 and 4 while in system management mode.
Which document are we talking about?
I'm afraid it doesn't work. Maybe I can find something in the AMD Elan
documentation. Would a fence make sense?