Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing

[FUJITA Tomonori]

On Fri, 19 Sep 2008 19:43:39 +0200
Joerg Roedel <joro@xxxxxxxxxx> wrote:

> Hi All,
> 
> FUJITA mentioned that I forgot to discuss this patch with you guys, the
> implementers and maintainers for Intel VT-d and Calgary IOMMU drivers. I
> would like to hear your opinion on that patch. He is right with that.
> The patch is already in tip/iommu but can easily be reverted if there
> are fundamental objections.
> The patch basically moves the iommu=fullflush and iommu=nofullflush
> option from the GART code to pci-dma.c. So we can use these parameters
> in other IOMMU implementations too. Since Intel VT-d is implementing
> also lazy IO/TLB flushing it would benefit from this generic parameter
> too. I am not so sure about Calgary, but we have other parameters for
> iommu= which doesn't affect all hardware IOMMUs.

nofullflush is pointless. It doesn't change any kernel behavior. Yes,
GART has it and we can't remove it because we exported it to
users. But please don't add such pointless option to the generic
options just for GART compatibility.

fullflush might be useful as a generic option to disable lazy IOTLB
flushing. But I'm not sure that Calgary uses it. VT-d already has
'strict' option for it and we can't change it. If VT-d wants to
support both 'strict' and 'fullflush' for disabling lazy IOTLB
flushing, it would make sense. But if VT-d doesn't want, it is useful
only for GART and AMD IOMMU. If so, I don't think that it is very
useful but I'm not against adding it.
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