On Tue, Oct 07, 2008 at 02:09:12PM -0700, H. Peter Anvin wrote:Venki Pallipadi wrote:For Intel 7400 series CPUs, the recommendation is to use a clflush on theThis seems very expensive. It really makes me wonder if it wouldn't
monitored address just before monitor and mwait pair [1]. This clflush makes
sure that there are no false wakeups from mwait when the monitored address
was recently written to.
[1] "MONITOR/MWAIT Recommendations for Intel Xeon Processor 7400 series"
section in specification update document of 7400 series
http://download.intel.com/design/xeon/specupdt/32033601.pdf
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@xxxxxxxxx>
just be better to either declare monitor/mwait non-functional on this
chip, or make sure that mwaits can handle false wakeups.
mwait can handle false wakeups. Today we wake backup all the way and find
out there is nothing to do and go back to idle. And second time around this
false wakeup does not happen as we do not write to monitored address in the
interim. The problem we saw was the places where we try to look at how
long each idle period was and take power management decision for the next idle.
Such algorithms get confused with false wakeups.
Yes. Other alternative is to disable mwaits altogether on these CPUs. I can
send a patch to do that. But, the patch will be somewhat more complicated
as kernel advertises the MWAIT capability to firmware with a ACPI _PDC method
and BIOS has to then give IO port based C2 for us to use in such case.
Avoiding mwait just for C1 is easy though.