Re: Fail to early boot with v2.6.27-rc2 to at least v2.6.29-rc2 dueto dc1e35c

[H. Peter Anvin]

Valdis.Kletnieks@xxxxxx wrote:
> On Mon, 19 Jan 2009 13:57:36 PST, Suresh Siddha said:
> 
>> Though the bios is the culprit and this option will severely limit
>> the cpu capabilities that OS can take advantage of, OS should fallback
>> to a safer mode. I will have a patch for it.
>>
>> Also, I wonder, if we should complain/scream during boot if we find only
>> fewer cpuid levels on modern generation cpu's.
> 
> I think a KERN_INFO "Core2 E9700 expected 6 cpuid levels, got 4"
> would possibly be a good idea.
> 
> Might be a good idea to check what happens under VMWare and similar though, it
> looks like the type of thing a hypervisor is likely to do something odd to us...

I think a much better idea is to just clear the MSR bit.  Attached is a
patch to do exactly that, which I will commit after testing.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 8ea6929..1107015 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -29,6 +29,16 @@
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
+	u64 misc_enable;
+
+	/* If MSR_IA32_MISC_ENABLE exists, unmask CPUID levels if masked */
+	if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable)) {
+		if (misc_enable & (1 << 22)) {
+			misc_enable &= ~(1 << 22);
+			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+		}
+	}
+
 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
 		(c->x86 == 0x6 && c->x86_model >= 0x0e))
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);