RE: [PATCH B 06/10] OMAP3 pwrdm: add CORE SAR handling (for USBTLLmodule)

[Paul Walmsley]

Hi Richard,

On Wed, 28 Jan 2009, Woodruff, Richard wrote:

> > 34xx TRM Delta G->H notes that the CORE powerdomain has a hardware
> > save-and-restore (SAR) control bit for the USBTLL module, similar to
> > the USBHOST powerdomain SAR bit.  Split the existing core_34xx struct
> > powerdomain into two structs, one for ES1 and one for ES2, and add the
> > PWRDM_HAS_HDWR_SAR flag to the ES2 powerdomain.
> >
> > Signed-off-by: Paul Walmsley <paul@xxxxxxxxx>
> > Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
> > +
> > +/* No wkdeps or sleepdeps for 34xx core apparently */
> > +static struct powerdomain core_34xx_es2_pwrdm = {
> > +     .name             = "core_pwrdm",
> > +     .prcm_offs        = CORE_MOD,
> > +     .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
> >       .pwrsts           = PWRSTS_OFF_RET_ON,
> >       .dep_bit          = OMAP3430_EN_CORE_SHIFT,
> > +     .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
> >       .banks            = 2,
> >       .pwrsts_mem_ret   = {
> >               [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
> 
> TLLSAR is not functional till ES3.1 (and beyound).  Is it possible to flag it this way?

Yes, it's easy in this case.  Thanks for the note.  I will send along an 
updated patch for this.

> If you try and use it your system will deadlock on 2nd OFF mode transition due to hardware bug.


- Paul
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