[tip:x86/cpu] x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it

[Andreas Herrmann]

Commit-ID:  bda869c614c937c318547c3ee1d65a316b693c21
Gitweb:     http://git.kernel.org/tip/bda869c614c937c318547c3ee1d65a316b693c21
Author:     Andreas Herrmann <andreas.herrmann3@xxxxxxx>
AuthorDate: Thu, 9 Apr 2009 15:05:10 +0200
Committer:  Ingo Molnar <mingo@xxxxxxx>
CommitDate: Fri, 10 Apr 2009 14:21:40 +0200

x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it

AMD family 0x11 CPU doesn't support the feature.

Some AMD family 0x10 CPUs do not support it or have an erratum, see
erratum #382 in "Revision Guide for AMD Family 10h Processors, 41322
Rev. 3.40 February 2009".

Signed-off-by: Andreas Herrmann <andreas.herrmann3@xxxxxxx>
CC: Mark Langsdorf <mark.langsdorf@xxxxxxx>
Cc: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>
LKML-Reference: <20090409130510.GG31527@xxxxxxxxxxxxxxxx>
Signed-off-by: Ingo Molnar <mingo@xxxxxxx>


---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 483eda9..7240126 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -291,6 +291,14 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
 	if (index < 3)
 		return;
+
+	if (boot_cpu_data.x86 == 0x11)
+		return;
+
+	/* see erratum #382 */
+	if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
+		return;
+
 	this_leaf->can_disable = 1;
 }
 
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