Re: [PATCH -tip 3/6 V4.1] x86: instruction decorder API

[H. Peter Anvin]

Masami Hiramatsu wrote:
> Hmm, I have an idea about instruction table. Usually, instruction tables
> are encoded with code defined by each decoder/emulator. This method
> will show their internal code directly, and is hard to maintain when
> the opcode map is updated. Instead of that, I'd like to suggest using
> the expressions in the opcode maps in a vender's genuine document (in
> this case, Intel/AMD's manual) or www.sandpile.org for instruction
> tables.

Yes, we discussed this at the Collab Summit.  I think it's the only sane 
thing.

> e.g.
>
> const insn_attr_t onebyte_attr_table[ATTR_TABLE_SIZE] = {
> /* 0x00-0x0f */
> AT2(Eb,Gb), AT2(Ev,Gv),  AT2(Gb,Eb),  AT2(Gv,Ev),
> AT2(AL,Ib), AT2(rAX,Iz), AT2(ES,i64), AT2(ES,i64),
> AT2(Eb,Gb), AT2(Ev,Gv),  AT2(Gb,Eb),  AT2(Gv,Ev),
> AT2(AL,Ib), AT2(rAX,Iz), AT2(CS,i64), AT(ESC),
> ...
>
> Here, AT and AT2 macros are defined as follows:

I would suggest using an actual parser, rather than relying on cpp for 
this.  The parser will be much more powerful, and will make it much 
easier to change data structure radically as we discussed.

	-hpa
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