Re: [PATCH -tip 3/6 V4.1] x86: instruction decorder API

[Masami Hiramatsu]

H. Peter Anvin wrote:
> Jim Keniston wrote:
>> It looks like AT2(Ev,Gv) would yield the same bits as AT2(Gv,Ev).  It'd
>> be nice not to lose the operand-order information.  And we'd have to
>> make clear whether which notation we're using -- src,dest as in the gnu
>> assembler, or dest,src as in the AMD (and Intel?) manuals.
>>
> 
> Since the information would come from the manuals, I would recommend 
> following them (dst first.)
>

Hi Peter and Jim,

Now what I'm doing is making opcode tables like this.

Table: 1-byte opcode
Alias: none
00: ADD Eb,Gb
01: ADD Ev,Gv
02: ADD Gb,Eb
03: ADD Gv,Ev
04: ADD AL,Ib
05: ADD rAX,Iz
06: PUSH ES (i64)
07: POP ES (i64)
08: OR Eb,Gb
09: OR Ev,Gv
0a: OR Gb,Eb
0b: OR Gv,Ev
0c: OR AL,Ib
0d: OR rAX,Iz
0e: PUSH CS
0f: 2-byte escape
...

and a parser script which parses them into,

const insn_attr_t primary_table[INAT_TABLE_SIZE] = {
	[0x04] = INAT_IMM(IMM_SIZE_BYTE)
	[0x05] = INAT_IMM(IMM_SIZE_VWORD32)
	[0x0c] = INAT_IMM(IMM_SIZE_BYTE)
	[0x0d] = INAT_IMM(IMM_SIZE_VWORD32)
	[0x0f] = INAT_ESC(IMM_ESC_2BYTE)
...

(note, instructions which has no attributes for decoder, are just ignored)


By the way, I'm worried about legal things of Intel's instruction
encoding expressions. Would you think there is any problem if we
have those tables in the kernel tree?

Thanks,

-- 
Masami Hiramatsu

Software Engineer
Hitachi Computer Products (America) Inc.
Software Solutions Division

e-mail: mhiramat@xxxxxxxxxx

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