RE: [PATCH] fsldma: use PCI Read Multiple command

[Liu Dave-R63238]

> Here's a few results from DMA tests between two
> MPC8349EA boards housed in a CPCI chassis.
> 
> 1. DMA mode register (DMAMRn)
>     PCI read command (PRC, bits 11:10)
> 
>     a) DMAMRn[PRC] = 00 = PCI Read
> 
>        The PCI read command is 6h on the PCI bus.
>        For DMA lengths of less than 1 cache line (32-bytes)
>        the DMA controller will generate a PCI 6h command.
>        However, for lengths of 32-bytes and higher, the
>        DMA controller actually generates a PCI Read Line (Eh)
>        command.
> 
>        Freescale indicated that this 'change of PCI command code'
>        functionality is an undocumented 'feature', there to
>        improve performance for longer read lengths.
> 
>     b) DMAMRn[PRC] = 01 = PCI Read Line
> 
>        Generated the PCI command code for PCI read line (Eh),
>        regardless of DMA length.
> 
>     c) DMAMRn[PRC] = 10 = PCI Read Multiple
> 
>        Generated the PCI command code for PCI Read Multiple (Ch),
>        regardless of DMA length.

Good summary!

For the DMA PCI read/line/multi-line is outbound transaction.
So according to your experiment, the 8349 PCI controller(as master)
attemp to streaming/combining the outbound transaction(treated as
prefetchable
space). 
IIRC, the early 8349EUM has the bit[2]-SE in the POCMRn
register, and is removed now. Not sure if it does function.
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