Re: One question about perf_counter on IA

From: Ingo Molnar
Date: Wed May 27 2009 - 10:46:56 EST

* Yong Wang <> wrote:

> I noticed that the LVT error register is masked and then unmasked
> during perf_counter initialization on IA in
> arch/x86/kernel/cpu/perf_counter.c
> void perf_counters_lapic_init(int nmi)
> {
> u32 apic_val;
> if (!x86_pmu_initialized())
> return;
> /*
> * Enable the performance counter vector in the APIC LVT:
> */
> apic_val = apic_read(APIC_LVTERR);
> apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
> if (nmi)
> apic_write(APIC_LVTPC, APIC_DM_NMI);
> else
> apic_write(APIC_LVTERR, apic_val);
> }
> Why is this needed? Is this documented somewhere in the spec? I
> tried commenting out the masking and unmasking operations and I
> did not any error interrupt generated.

i think a spurious error irq can be triggered due to APIC_DM_NMI
having zero for the vector bit. If we switch between irq and nmi
mode frequently then there could be racy situations.

Not that having an error irq would hurt much ...

Note, in the current code we essentially always use NMI mode, the
cleanups just have not propagated through fully yet. Feel free to
send a patch for this!

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