Re: [RFC PATCH] pccard: configure CLS on attach
From: Benjamin Herrenschmidt
Date: Thu May 28 2009 - 02:48:25 EST
On Thu, 2009-05-28 at 08:11 +0900, Tejun Heo wrote:
> Matthew Wilcox wrote:
> > On Wed, May 27, 2009 at 10:32:45PM +0900, Tejun Heo wrote:
> >> THIS IS A RFC PATCH, SO NO SOB. PLEASE DON'T APPLY YET.
> > This breaks CONFIG_PPC64, fwiw. We'll want to stub out
> > pci_set_cacheline_size() for the PCI_DISABLE_MWI case too.
> Right, thanks for spotting it.
> > I don't know what PPC machines have Cardbus slots, presumably some
> > Macs do. I don't know whether firmware takes care of configuring the
> > Cacheline Size register for Cardbus hotplug or not. So we may want to
> > include pci_set_cacheline_size() in the !MWI build, or not. Ben, Paul?
Right, 32-bit Mac laptops mostly, maybe embedded stuff too. On these we
definitely want to configure stuff properly from the kernel.
> ppc64 is also missing PCI_CACHE_LINE_SIZE so pci_set_cacheline_size()
> can't be built as-is.
Well, the PCI cache line size would be a runtime thing. There are some
"issues" though on some HT platforms that I don't completely remember,
it really all depends on what the machine actually is.
So I'll need to have a look at the actual patch set to figure out
how we want to deal with it.
> BTW, on x86, pci_cache_line_size isn't
> configured like other pci devices on many machines, which doesn't harm
> correctness but still... CLS being the same for all devices coming
> down from the same root bridge, maybe we can do away with the current
> logic and just take it from the upstream pci bridge?
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