[PATCH 19/62] Blackfin: fix detection of cached L2 SRAM

[Mike Frysinger]

Make sure our bfin_addr_dcachable() function flags cached L2 SRAM properly
else memory easily goes unflushed when working with DMA.

Signed-off-by: Mike Frysinger <vapier@xxxxxxxxxx>
---
 arch/blackfin/include/asm/cacheflush.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index d7726ab..94697f0 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -108,6 +108,11 @@ static inline int bfin_addr_dcachable(unsigned long addr)
 		addr >= _ramend && addr < physical_mem_end)
 		return 1;
 
+#ifndef CONFIG_BFIN_L2_NOT_CACHED
+	if (addr >= L2_START && addr < L2_START + L2_LENGTH)
+		return 1;
+#endif
+
 	return 0;
 }
 
-- 
1.6.3.1

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