Re: [tip:perfcounters/core] perf_counter: x86: Fix call-chainsupport to use NMI-safe methods
From: Mathieu Desnoyers
Date: Mon Jun 15 2009 - 14:39:27 EST
* Ingo Molnar (mingo@xxxxxxx) wrote:
> * Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxx> wrote:
> > Hrm, would it be possible to save the c2 register upon nmi handler
> > entry and restore it before iret instead ? This would ensure a
> > nmi-interrupted page fault handler would continue what it was
> > doing with a non-corrupted cr2 register after returning from nmi.
> > Plus, this involves no modification to the page fault handler fast
> > path.
> I guess this kind of nesting would work too - assuming the cr2 can
> be written to robustly.
> And i suspect CPU makers pull off a few tricks to stage the cr2 info
> away from the page fault entry execution asynchronously, so i'd not
> be surprised if writing to it uncovered unknown-so-far side-effects
> in CPU implementations.
> If possible i wouldnt want to rely on such a narrowly possible hack
> really - any small change in CPU specs could cause problems years
> down the line.
> The GUP based method is pretty generic though - and can be used on
> other architectures as well. It's not as fast as direct access
I guess. However, having the ability to call module code in NMI handler
context without having to fear for page fault handler re-entrancy (on
x86 32) seems like an interesting overall simplification of nmi-handler
rules. It is currently far from trivial to write code aimed at NMI
handler context. I mean.. LTTng should not have to run
vmalloc_sync_all() after loading its modules as it currently does.
Maybe it would be worth trying the save/restore cr2 approach and test to
figure out how a large variety of machines react. The fact is that
hypervisor code already writes into the cr2 register :
"mov %%"R"ax, %%cr2 \n\t"
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