Re: [VIA Support] Instruction timing and cache coherency issues

[Pavel Machek]

On Sun 2009-08-02 21:08:51, Harald Welte wrote:
> On Thu, Jul 30, 2009 at 11:08:04AM +0200, Pavel Machek wrote:
> 
> > > Diddling with the things I have found that either "fix" or "work around"
> > > the various timing / cache coherency issues - - -
> > > Aw, so - found how to affect the timing issues sufficiently so that Linux
> > > would panic dump rather than deadlock on the troublesum combination - -
> > > *Functionally the same* panic backtrace that FreeBSD is showing.
> > > 
> > > @H.W.  Download the FreeBSD-8.0-beta2 and try running it on your Cloudbook
> > > and HP-2133, you can see what is happening.  Then you might have a word or
> > > two with the silicon growers.
> > > 
> > So... you believe you have pinpointed bug in their cpu design?
> 
> I would not preclude that, but I think what might be more likely is that there
> is some difference between how Intel and how VIA/Centaur behaves in a certain
> situation, or the compiler making a wrong assumption about what it can do or
> cannot do (remember e.g. for the VIA C3 there was no cmpxchg8, but gcc uses
> it in case you compile with i686 optiomization).

I'd expect any difference in behaviour (modulo timing, extensions, and
cpuid) between Intel 486 and VIA C3 to be VIA bug, because VIA is
supposed to be Intel 486 compatible, no?

If not, where is behaviour of VIA cpus specified? Will we have to
compare 1000s of pages of instruction manuals to see where the traps lie?

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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