Re: [PATCH v2] Staging: Correct tsi-148 VME interrupt free routine

[Jiri Slaby]

On 08/05/2009 06:38 PM, Martyn Welch wrote:
>  	if (tsi148_bridge->irq[level - 1].count == 0) {
> -		tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
> -		tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
> -		iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
> -
>  		tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
>  		tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
>  		iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
> +
> +		tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
> +		tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
> +		iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);

I have no idea what the registers do and I suppose it's behind some PCI
bridge anywhere. If it is not true, ignore the further.

Is it OK that the second write to INTEO doesn't reach the device before
you set func to NULL? I mean, is it enough to prevent the interrupt
raising only by twiddling INTEN? Otherwise you need to put some read
right here to push non-completed writes on bridges (flush posted
writes). (I mentioned this in the former mail too.)

Otherwise looks good.

>  	}
>  
> +	tsi148_bridge->irq[level - 1].callback[statid].func = NULL;
> +	tsi148_bridge->irq[level - 1].callback[statid].priv_data = NULL;
> +
>  	/* Release semaphore */
>  	up(&(vme_irq));
>  }

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